In recent years, attention has been given to asynchronous frequency dividers to achieve high speed and low power requirements. For example, a paper by Patrik Larsson published in the “IEEE Journal of Solid-State Circuits”, Vol. 31, No. 5, May 1996, discloses the frequency divider shown in FIG. 1.
As shown, the frequency divider has a clock pre-processor circuit 101 that blocks the clock for odd division, a divide-by-two circuit 102 that divides the input clock frequency by a factor of 2, a series of identical bit-cells 103-105, a one detect circuit 106 that detects whether all stages are at the logic-high state, and a D flip-flop 107.
The input clock CLK is applied to the clock pre-processor circuit 101, and to the D flip-flop 107 via an inverter 108. The output 110 of the pre-processor circuit 101 is passed to the divide-by-two circuit 102. The Q-output 111 of the divide-by-two circuit 102 is connected to the input of the first bit-cell 103.
Each bit-cell has two outputs: CLKi and OUTi. The first output OUTi of each bit-cell and the QN output of the divide-by-two circuit 102 are fed to the one-detect-circuit 106, while the second output CLKi of each bit-cell is fed to the input clock of the next bit-cell.
The one-detect-circuit 106 has two sets of inputs. The first set of inputs is the data inputs P1 to Pn while the second set of inputs receives the OUTi outputs of the bit-cells. The first set of inputs is used to determine the bits to be used from the second set of inputs for determination of the output state of the one-detect-circuit 106. The one-detect-circuit 106 starts detection of the state of the data input starting from the MSB of the data input. As soon as it encounters the first logic-high data input it logically ANDs the OUTi outputs of bit-cells numbered from that data input to the remaining data inputs (i.e., the LSB data input) to get the final output of the one-detect-circuit 106. If all the data inputs P1 to Pn are at the logic-low state, then the output of the one-detect-circuit 106 is at the same state as that of the QN output of the divide-by-two circuit 102.
The one-detect-circuit 106 outputs a logic-high signal when the output OUTi of each bit-cell and the QN output of the divide-by-two circuit 102 are at the logic-high state. The output of the one-detect-circuit 106 is fed to the input of the D flip-flop 107. The D flip-flop 107 receives its clock from an inverter 108, so as to receive an inverted input clock.
A standard D flip-flop 107 is used in this counter. It has one data-input D, one clock-input CLK, and two outputs Q and QN. The output of the one-detect-circuit 106 is connected to the D input of the D flip-flop 107. The input clock to the frequency divider is inverted and this inverted output 120 is fed to the CLK input of the D flip-flop 107. The QN output 121 of the D flip-flop is connected to the CLK_BLOCK input of the clock-pre-processor circuit. The Q output 122 of the D flip-flop is coupled to the final output pin of the counter. The LSB of the input data bits P0 is inverted and connected to the POBAR input of the clock pre-processor circuit.
FIG. 2 shows the construction of the divide-by-two circuit. The divide-by-two circuit has one CLK input 401 and two outputs: Q 402 and QN 403. It divides the input clock frequency by a factor of 2.
FIG. 3 shows the clock pre-processor circuit. The circuit has two control inputs, one clock input, and one clock output. The control inputs of the circuit are POBAR 052 and CLK_BLOCK 053, while CLK_IN 051 is the input clock and CLK_OUT 054 is the output clock that is fed to the divide-by-two circuit 102. When both the control inputs of the clock pre-processor circuit are logic-low, its output is logic-high. But when any of the control inputs is logic-high, the output of the clock preprocessor circuit is the inverted value of the input clock.
FIG. 4 shows one bit-cell circuit. It comprises five inputs: CLKi−1 501, Pi 502, LD 503, CLKi+1 504, OUTi−1 505. It also comprises two outputs: CLKi 507 and OUTi 508. CLKi+1 504 is connected to CLKi of the next stage bit-cell, while CLKi−1 501 is connected to CLKi of the previous stage bit-cell. Similarly, OUTi−1 505 is connected to OUTi of the previous stage bit-cell.
Within the bit-cell there is a net LdMem 509. Whenever there is logic-low at P1, logic-low at LD, and logic-high at OUTi, then LdMem goes logic-high. When CLKi+1 and OUTi−1 go high, then net Idout 506 goes logic-low, which in turn forces CLKi to logic-low and OUTi to the logic-high state. As OUTi goes logic-high, LdMem goes logic-low, which in turn forces ldout to logic-high. In normal conditions, when LdMem is at the logic-low state, the bit-cell works as a divide-by-two circuit. It divides the input clock frequency at CLKi−1 by a factor of 2 and gives the output at CLKi and OUTi.
However, according to the structure of this frequency divider, if Q of the first divide-by-two 102 is at logic-low, the output of the clock pre-processor 110 is at logic-high, and all the control inputs of the clock pre-processor circuit are at the logic-low state, then it will get stuck in that state and can never come out. Apart from that, the architecture of the bit-cell circuit is also complex in order to latch the Ldout signal.